https://cpudev.org/w/index.php?action=history&feed=atom&title=Transport_triggered_architecture 2026-04-23T16:28:14Z Revision history for this page on the wiki MediaWiki 1.36.1 https://cpudev.org/w/index.php?title=Transport_triggered_architecture&diff=34&oldid=prev 2025-05-03T21:49:42Z

<p>Created page with &quot;A &#039;&#039;&#039;Transport triggered architecture&#039;&#039;&#039; (&#039;&#039;&#039;TTA&#039;&#039;&#039;) is a <a href="/w/index.php?title=One_instruction_set_computer&amp;action=edit&amp;redlink=1" class="new" title="One instruction set computer (page does not exist)">one instruction set computer</a> which only moves data between various function units. It is a very minimal, simple a...&quot;</p> <p><b>New page</b></p><div>A &#039;&#039;&#039;Transport triggered architecture&#039;&#039;&#039; (&#039;&#039;&#039;TTA&#039;&#039;&#039;) is a [[one instruction set computer]] which only moves data between various function units. It is a very minimal, simple and flexible type of architecture.<br /> <br /> A typical TTA consists of one or more transport buses, with various units attached to these buses. Each instruction configures the source and destination, i.e. moves data over the buses.<br /> Certain data movements may trigger an attached unit to perform an action, hence &#039;&#039;transport triggered&#039;&#039;.<br /> <br /> TTAs expose a lot of microarchitectural details which are otherwise abstracted in more typical architectures. Due to this, (assembly) code written for a specific TTA tends to be non-portable.<br /> <br /> [[File:Transport-triggered architecture example.png|thumb|An example of a TTA. Note that many more configurations are possible, including with multiple transport buses.]]</div>

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