Bare Bones ISA

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This is the ISA implemented by most Bare Bones tutorials. In order to reduce complexity, it's nothing more than an 8-bit RISC ISA.

Basic Parts

The CPU is connected to three peripherals: a 128-byte RAM device mapped at 0x00, a single-byte TTY device mapped at 0x80 and a 64-byte ROM device mapped at 0xC0. The TTY device takes bytes sequentially one-at-a-time and outputs them in the same order.

Registers

There are 16 explicit general-purpose 8-bit registers, named R0 to R15.

There is 1 implicit instruction-pointer 8-bit register. Its initial value is 0xC0, so the CPU starts execution from the start of ROM.

Instructions

There are six valid instructions: NOP, HLT, LDA, STA, LDI and ADD. All of them are explained in the following subsections. An instruction word is 16-bit (instruction format tables in the following subsections assume big-endian).

NOP

No operation, except of incrementing instruction-pointer register to the next instruction.

Bits Name Description
15:12 OPCODE Always 0b0000
11:0 RESV Reserved - Don't care

HLT

Halt, stop execution.

Bits Name Description
15:12 OPCODE Always 0b0001
11:0 RESV Reserved - Don't care

LDA

Load from address.

Bits Name Description
15:12 OPCODE Always 0b0010
11:8 DEST Index of destination register, i.e. the one where the loaded value will be written to
7:4 SRC Index of source register, i.e. the one containing the address of the loaded value
3:0 RESV Reserved - Don't care

STA

Store to address.

Bits Name Description
15:12 OPCODE Always 0b0011
11:8 DEST Index of destination register, i.e. the one containing the address of the stored value
7:4 SRC Index of source register, i.e. the one where the stored value will be read from
3:0 RESV Reserved - Don't care

LDI

Load immediate.

Bits Name Description
15:12 OPCODE Always 0b0100
11:8 DEST Index of destination register, i.e. the one where the loaded value will be written to
7:0 SRC The loaded immediate value

ADD

Perform an addition.

Bits Name Description
15:12 OPCODE Always 0b0101
11:8 DEST Index of destination register, i.e. the one where the result will be written to
7:4 SRC1 Index of first source register
3:0 SRC2 Index of second source register