Bare Bones in VHDL
This page or section is in progress. It may therefore not be complete and/or accurate.
This tutorial assumes you already confident in your VHDL skills, as well as, have an understanding of Boolean Algebra, combinational logic, sequential logic, as well as, understanding of binary and hexadecimal numeric systems.
The processor implements a really simple datapath, as shown in the image on the right. There are two internal buses, named X and Y. Bus X connects the register file with the ALU input registers A and B. Bus Y connects the ALU output register C to the register file. The ALU registers also act as the Memory Address Register (A) and Memory Data Register (write: B, read: C) for memory accesses, this simplifies the control unit and removes the need for extra registers.
The computer follows the Von Neumann architecture, which means it has a single memory space for both data and instructions. The Bare Bones ISA specification also specify a 128-byte RAM module, a 64-byte ROM module and a TTY device. Memory is divided into regions as follows.
|0x00 - 0x7F||RAM|
|0x81 - 0xBF||Reserved|
|0xC0 - 0xFF||ROM|
All signals will be UPPERCASE and named following this scheme:
- I_* : in signals
- Q_* : out signals
- L_* : local signals
- any other prefix to signify that it is a local signal, but is driven by/read by a certain component.
Top Level Design
The CPU will be broken down into several more sizeable chunks, to make life a lot easier.
For testing purposes we will also have RAM, ROM and TTY components. Finally these, and the cpu_top component are put together in a testbench entity. To run this testbench entity we need GHDL. First we analyze all VHDL files in the src/ and test/ directories.
ghdl -a --ieee=synopsys -fexplicit --workdir=simu --work=work src/*.vhd test/*.vhd
Then we elaborate the testbench entity.
ghdl -e --ieee=synopsys -fexplicit --workdir=simu --work=work testbench
And finally we run the testbench for 40 microseconds, the results are dumped to results.vcd.
ghdl -r --ieee=synopsys -fexplicit --workdir=simu --work=work testbench --vcd=results.vcd --stop-time=40us --ieee-asserts=disable --stats
All code is available here
|Bare Bones in VHDL: Part 2|