"CISC" stands for "Complex Instruction Set Computer". As its name indicates, instructions of CISC architectures have more work to do than instructions of RISC architectures.
In the 1970s, the first microprocessors implemented a CISC ISA. The main reasons for this were that:
- The hardware industry was more developed compared to the software industry - High-level programming languages weren't very widespread yet and most programmers were using assembly. Having a more complex ISA helped assembly programmers accomplish their task more easily, since more instructions could be mapped to high-level operations.
- Main memory was expensive and constrained - A higher code density helped quite a lot in memory usage.
However, during the late 1970s and early 1980s, high-level programming languages became the de-facto standard way of programming, so complex ISAs weren't needed anymore, since compilers would automatically translate operations into instructions from then on. It was also observed that most programs (either written in assembly by hand or compiled by a compiler from a high-level language) didn't make use of all CISC instructions.
As for main memory, it became cheaper, allowing it to reach bigger sizes. Simultaneously, data started to be the primary issue in memory usage in most scenarios. These two factors, made code density not longer a strict requirement.
The new design was named "RISC" and the older design was retro-actively named "CISC".
Some companies (e.g. Intel) continued with CISC ISAs. However, most of the other chip makers adopted RISC design philosophies.
CISC ISAs/CPUs present some advantages over RISC ISAs/CPUs.
- Less instructions needed to complete a task - Many tasks that take a couple of instructions in RISC architectures can be done in one instruction in a CISC architecture. This also helps assembly programmers.
- Higher code density - Code density, historically, has allowed for minimised memory usage. However, this consideration reappears, but now with cache memory, especially with repeatedly executed code. The main outcome of higher code density nowadays is less cache misses.
CISC ISAs/CPUs however have their disadvantages too.
- Usually a single instruction needs more time to complete - Due to more complex instruction formats and usually varied instruction lengths, fetch and decoding can take more time than in RISC designs.
- Harder to pipeline - Due to the possible presence of memory operands in almost every instruction, it is much harder to do dependency checking and, as a result, it is also harder to pipeline the CPU. Besides, interacting with memory usually stalls the pipeline.
- More complex hardware implementation - A more complex hardware implementation has more room for bugs, is more expensive and has less space for caches and/or multiple cores. To reduce space needed for the main components of each core, microcode is almost always used.
- Harder to write a compiler for - It's easier to do high-level language translation to a RISC assembly/machine language than to a CISC assembly/machine language. It's also been observed that most compilers don't make use of most of specialised instructions.
Intel and AMD has shown us that money, smaller fabrication processes and yet more complex solutions (e.g. Out-of-Order Execution) can overcome speed-related issues.
Historical Notes on CISC and RISC