CMOS is an abbreviation for Complementary Metal-Oxide-Semiconductor, it is a technology for constructing integrated circuits.
Typical CMOS design style uses complementary, symmetrical pairs of p-type and n-type MOSFETs.
The primary reasons that CMOS became the most used technology in very-large-scale integration (VLSI) circuits are its high logic function density and its high noise immunity and lower power consumption. The circuit only draws significant power during switching between on and off states, since one of the transistors of the pair is always off. As such, CMOS devices produce less heat than other forms of logic.
n+ is n-type diffusion in a p-type substrate, p+ is p-type diffusion in an n-type substrate.
Note that there is no physical difference between source and drain.
Because of the physical structure, the n-type always has to be connected to Vss (ground) and the p-type to Vdd.
- When the NMOS drain is connected to Vdd, the transistor will be in saturation (Vds > Vgs - Vth). If Vg is high the maximum output will be Vg - Vth. Passing 1 from drain to source is poor for NMOS.
- When the PMOS source is connected to Vdd and Vg is low, the drain can go up to Vdd. Passing 1 from source to drain is well for PMOS.
- When the PMOS drain is connected to Vss, the drain will be Vth greater than Vgs. Passing 0 from drain to source is poor for PMOS.
- When the NMOS source is connected to Vss and Vg is high, the drain can go down to Vss. Passing 0 from source to drain is well for NMOS
The body of the p- and n-type transistors should be connected to Vdd and Vss respectively, to prevent latch-up.
Latch-up is a type of short circuit which can occur in an IC. It is the creation of a low-impedance path between the power rails (Vdd and Vss), triggering a parasitic structure, which usually destroys the chip. The combination of n-well/p-well and substrate can lead to the creation of an n-p-n-p structure, when one of the two transistors in this structure gets forward-biased, it feeds the base of the other transistor. The positive feedback increases the current until the circuit fails or burns out.
By adding a layer of insulating oxide (called a trench) surrounding both the NMOS and PMOS devices, the parasitic structure can be broken. This way the devices are resistant to latch-ups.
Most silicon-on-insulator circuits are inherently resistant to latch-up, since latch-up is the low impedance connection between power rails via n-/p-wells.
MOSFETs are made up of two PN-junctions as visible in the images in physical structure. Every PN-junction is a diode, where the anode is the p-type Si and the cathode is the n-type Si. To prevent latch-up, the body-source and body-drain diodes should be kept reverse-biased;
- For the n-type this means that the voltage over Drain and Body (Vdb) should be positive (or zero), which is only possible when the Body voltage (Vb) is lower than or equal to the Drain voltage (Vd). So, all the p-substrates are connected to Vss.
- For the p-type this means that the voltage over Body and Drain (Vbd) should be positive (or zero), which is only possible when Vb is higher than or equal to Vd. So, all the n-substrates are connected to Vdd.