Magic VLSI Layout Tool
The source code can be easily downloaded from the website mentioned above. Bundled with the source code comes a file named INSTALL with detailed instructions on compiling the source code. For the lazy, the following will suffice.
./configure make make install
Arch Linux has a precompiled package for Magic.
sudo pacman -Sy magic
The application can't run natively on Windows, but can be run with tools like Cygwin. Installation instructions on Cygwin can be found here.
Magic has a steep learning curve, and comes bundled with a dozen tutorial layouts and a basic tutorial can be found on the website.
Making CMOS transistors
Before attempting to make these transistors make sure you understand the basic controls and commands, as these will be used without explanation in this section.
The structure of the transistors can be seen in the image on the right. The Base shown in that image is to prevent latch-up
- Begin with a line of poly-silicon (the Gate) of at least 7x2 lambda (this is the absolute minimum for a transistor, though you may expand it to make sure you stay away from metal contacts)
- Through the middle of this line, draw p-diffusion of 3x8, where the parts sticking out of the poly-silicon are the source and drain. If you did everything right you will see that where the poly-silicon and p-diffusion cross a striped pattern is shown.
- Finally you need to draw an n-well of at least 10x10, under the transistor. Essentially, the transistor is now complete, but we will be adding metal contacts for power and input/output.
- Now all that's left is to make pads for metal contacts. The minimum size for a poly-metal contacts is 4x4 lambda, for pdiff-metal that is 5x5. As shown in the image on the right. (purple is poly-metal, blue is pdiff-metal)
Note that the poly-silicon only needs one metal contact as it is one single wire, whereas the source and drain are physically separated.
The N-type transistor has the same basic structure as the P-type, although the materials differ.
- n-well -> p-well
- p-diffuse -> n-diffuse (green)
- pdiff-metal contact -> ndiff-metal contact (light-blue)
Making a NOT-gate
A CMOS NOT-gate consists of one N-type and one P-type transistor in series, the transistors share the Gate. The Source of the N-type is always (for all circuits, not only for the NOT-gate) connected to Vss (ground), while the Source of the P-type is always connected to Vdd.
In larger circuits, the Vss and GND would be larger power rails going strategically over the design in a higher metal layer. The power rails are normally also connected to the Base, which is an n-diff for P-type transistors and p-diff for N-type transistors (see CMOS)
One way of making capacitors is to use the two polysilicon layers in our process. We create a parallel plate capacitor with poly1 and poly2 ("electrode") forming the two parallel sides. The silicon dioxide between the two poly layers is thin enough to yield good capacitance values per unit area. This is called a poly-poly capacitor.
To calculate the area of the capacitor we need to know the capacitance per unit area. For the scna20_orb process this value is about 800 aF/lambda²
Area = C / 800 aF
This is the area of overlap of poly and electrode (poly2), the poly should extend 2 lambda beyond the sides of the electrode. So, for a 320 fF capacitor we get an electrode area of 400 lambda² or 20x20 lambda.
:box 2 2 22 22 :paint electrode :box 0 0 24 24 :paint poly
Then add terminals (4x4) of type capc and pc to the electrode and the poly respectively.
Magic layouts can be simulated with IRSIM. Doing so is quite simple:
First extract the root cell and all it's children.
Then convert the extracted cells to a format readable by IRSIM. The -L flag disables auxilliary .nodes files. The -R flag enables lumped resistance, -c is short for -cthresh, the capacitance threshold (in femtofarads). For other flags, or a more detailed explanation, take a look at the Magic Command Reference.
ext2sim -L -R -c 20 <root_cell>.ext
Now you can quit magic and launch IRSIM. The technology file specifies the parameters for the first-order timing check.
irsim <technology_file>.prm <root_cell>.sim
For a guide on using IRSIM, see the IRSIM page.
- This value was determined by trial and error, as the official value cannot be found anywhere. (Please confirm)