"RISC" stands for "Reduced Instruction Set Computer". As its name indicates, its instructions usually have less work to do compared to instructions of CISC architectures. Usually, the main goal of RISC ISAs is to reduce the "cycles per instruction" ratio.
In order to achieve their goal, RISC CPUs have various attributes:
- Load-store - Interacting with main memory is very slow compared to interacting with registers. For this reason, most instructions operate on registers (and possibly immediates), while having a handful of specialised instructions for interacting with main memory (usually only LOAD and STORE).
- Fixed instruction format - In order to simplify fetch and decode, instructions are usually placed on fixed (e.g. 32-bit) boundaries and have a fixed length and a fixed format.
- Usually fewer specialised instructions - Usually, but not always, RISC CPUs have a lower count of instructions, comprising only of opcodes for generalised tasks.
This comes in contrast to CISC ISAs which most CPUs had been using before RISC ISAs came around in the late 1970s.
RISC ISAs/CPUs feature various advantages over CISC counterparts.
- Faster execution of a single instruction - A single instruction needs less time to execute (usually one clock cycle, unless it's interacting with main memory).
- Easier to pipeline - Because the instruction length is fixed and because most instructions operate only on registers (and possibly immediates), it's much easier to do dependency checking and it's somewhat more rare for (optimised) code to stall the pipeline by interacting with memory (otherwise, Out-of-Order Execution can still help).
- Usually simpler hardware implementation - This means they have less space for bugs (although they still eventually happen), they are cheaper and have more space for caches and/or multiple cores.
- Facilitation of compiler's job - It's easier to do high-level language translation to a RISC assembly/machine language than to a CISC assembly/machine language. It's also been observed that most compilers don't make use of most of CISC specialised instructions.
RISC ISAs/CPUs don't come however without their disadvantages.
- Usually more instructions needed to complete a task - Examples may include performing an arithmetic operation between two memory values or loading a 64-bit immediate when the instruction length is only 32 bits.
- Lower code density - Due to "Usually more instructions needed to complete a task" and due to instructions having a fixed length (that's usually bigger than most CISC instructions length), machine code is less dense. This causes a higher main memory and cache memory usage, thus more frequent cache misses.