User Projects
From CPUDev Wiki
Here are listed user projects.
Contents
Instruction Set Architectures
Thunderstone ISA Mk I
| Name | Author | Bitness | Endianness | Type | Number of OPCODEs | Status | Website | |
|---|---|---|---|---|---|---|---|---|
| Thunderstone Mark I | Redgek(talk) | 8-bit word | 16-bit address | Big | RISC | 22 | Done | codebite.xyz |
Glauxosdever's Attempt-1
| Name | Author | Bitness | Endianness | Type | Status | Website |
|---|---|---|---|---|---|---|
| Attempt-1 | Glauxosdever (talk) | 8/16/32/64-bit | Small | RISC | In progress | User:Glauxosdever/Attempt-1 |
LC-4
| Name | Author | Bitness | Endianness | Type | Number of Opcodes | Status | Website |
|---|---|---|---|---|---|---|---|
| LC-4 | chibill (talk) | 16-bit | Big | RISC | 16 | In progress | [1]] |
CPU Implementations
LightningRock Mk I
| Name | Author | ISA | Tool | Language | Status | Website |
|---|---|---|---|---|---|---|
| LightningRock Mark I | Redgek (talk) | Thunderstone ISA Mk I | Logisim | N/A | Done | codebite.xyz |
RISC-V 64-bit pipelined implementation
| Name | Author | ISA | Tool | Language | Status | Website |
|---|---|---|---|---|---|---|
| RV64I-priv | gijswl (talk) | RV64I-priv | GHDL/GTKWave | VHDL | In progress | RV64I-priv |
