Difference between revisions of "Hardware Description Language"

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(Created page with "A <strong>hardware description language</strong>, or <strong>HDL</strong>, is a tool to describe the behavior of electronic circuits. While intended for simulation, most (all...")
 
(→‎List of HDLs: Add Calyx)
 
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This list is incomplete. Feel free to add more entries.
This list is incomplete. Feel free to add more entries.


<em>Please keep the list alphabetic.</em>
{|class="wikitable sortable"
 
|+ Caption text
* [https://www.chisel-lang.org/ Chisel]
|-
* [https://clash-lang.org/ Clash]
! Name !! Simulation !! Synthesis !! Allows non-synthesizable constructs
* [https://www.myhdl.org/ MyHDL]
|-
* [https://rust-hdl.org/ RustHDL]
| [https://calyxir.org/ Calyx]
* [https://github.com/SpinalHDL/SpinalHDL SpinalHDL]
| ?
| ?
| ?
|-
| [https://www.chisel-lang.org/ Chisel]
| ?
| ?
| ?
|-
| [https://clash-lang.org/ Clash]
| ?
| ?
| ?
|-
| [https://www.myhdl.org/ MyHDL]
| ?
| ?
| ?
|-
| [https://rust-hdl.org/ RustHDL]
| Yes
| Yes
| ?
|-
| [https://github.com/SpinalHDL/SpinalHDL SpinalHDL]
| Yes
| Yes
| ?
|}


== See also ==
== See also ==

Latest revision as of 11:29, 22 March 2025

A hardware description language, or HDL, is a tool to describe the behavior of electronic circuits.

While intended for simulation, most (all?) HDLs are also usable to synthesize physical circuits. However, beware some languages support constructs that cannot actually be translated to a physical circuit.

The most common HDL is Verilog, followed by VHDL. Many other HDLs are translated to Verilog under the hood.

Simulation

Verilator

Synthesis

Yosys

List of HDLs

This list is incomplete. Feel free to add more entries.

Caption text
Name Simulation Synthesis Allows non-synthesizable constructs
Calyx ? ? ?
Chisel ? ? ?
Clash ? ? ?
MyHDL ? ? ?
RustHDL Yes Yes ?
SpinalHDL Yes Yes ?

See also

External references