Difference between revisions of "Hardware Description Language"
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! Name !! Simulation !! Synthesis !! | ! Name !! Simulation !! Synthesis !! Allows non-synthesizable constructs | ||
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| [https://calyxir.org/ Calyx] | |||
| ? | |||
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| [https://www.chisel-lang.org/ Chisel] | | [https://www.chisel-lang.org/ Chisel] | ||
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| Yes | | Yes | ||
| Yes | | Yes | ||
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| [https://github.com/SpinalHDL/SpinalHDL SpinalHDL] | | [https://github.com/SpinalHDL/SpinalHDL SpinalHDL] | ||
| Yes | | Yes | ||
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Latest revision as of 11:29, 22 March 2025
A hardware description language, or HDL, is a tool to describe the behavior of electronic circuits.
While intended for simulation, most (all?) HDLs are also usable to synthesize physical circuits. However, beware some languages support constructs that cannot actually be translated to a physical circuit.
The most common HDL is Verilog, followed by VHDL. Many other HDLs are translated to Verilog under the hood.
Simulation
Synthesis
List of HDLs
This list is incomplete. Feel free to add more entries.
| Name | Simulation | Synthesis | Allows non-synthesizable constructs |
|---|---|---|---|
| Calyx | ? | ? | ? |
| Chisel | ? | ? | ? |
| Clash | ? | ? | ? |
| MyHDL | ? | ? | ? |
| RustHDL | Yes | Yes | ? |
| SpinalHDL | Yes | Yes | ? |
See also
External references
- Awesome Hardware Description Languages - a list of HDLs and associated tools