Difference between revisions of "Hardware Description Language"

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(Created page with "A <strong>hardware description language</strong>, or <strong>HDL</strong>, is a tool to describe the behavior of electronic circuits. While intended for simulation, most (all...")
 
(→‎List of HDLs: sortable table + feature matrix)
Line 17: Line 17:
This list is incomplete. Feel free to add more entries.
This list is incomplete. Feel free to add more entries.


<em>Please keep the list alphabetic.</em>
{|class="wikitable sortable"
 
|+ Caption text
* [https://www.chisel-lang.org/ Chisel]
|-
* [https://clash-lang.org/ Clash]
! Name !! Simulation !! Synthesis !! Type system
* [https://www.myhdl.org/ MyHDL]
|-
* [https://rust-hdl.org/ RustHDL]
| [https://www.chisel-lang.org/ Chisel]
* [https://github.com/SpinalHDL/SpinalHDL SpinalHDL]
| ?
| ?
| ?
|-
| [https://clash-lang.org/ Clash]
| ?
| ?
| ?
|-
| [https://www.myhdl.org/ MyHDL]
| ?
| ?
| ?
|-
| [https://rust-hdl.org/ RustHDL]
| Yes
| Yes
| Static, strong
|-
| [https://github.com/SpinalHDL/SpinalHDL SpinalHDL]
| Yes
| Yes
| Static, strong
|}


== See also ==
== See also ==

Revision as of 20:53, 21 March 2025

A hardware description language, or HDL, is a tool to describe the behavior of electronic circuits.

While intended for simulation, most (all?) HDLs are also usable to synthesize physical circuits. However, beware some languages support constructs that cannot actually be translated to a physical circuit.

The most common HDL is Verilog, followed by VHDL. Many other HDLs are translated to Verilog under the hood.

Simulation

Verilator

Synthesis

Yosys

List of HDLs

This list is incomplete. Feel free to add more entries.

Caption text
Name Simulation Synthesis Type system
Chisel ? ? ?
Clash ? ? ?
MyHDL ? ? ?
RustHDL Yes Yes Static, strong
SpinalHDL Yes Yes Static, strong

See also

External references

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