RISC vs CISC

Contemporary usage of the terms RISC and CISC is muddy, but originally referred to the amount of operations a single instruction could (or should) do.

For example, swapping values between a register and a memory location on a RISC machine may be done as:

ld.w  x3,[x2]    ; 1 cycle
st.w  [x2],x1    ; 1 cycle
mv    x1,x3      ; 1 cycle

Whereas on a CISC machine it might be done as:

xchg  x1,[x2]    ; 3 cycles

RISC cores tend to be smaller and simpler, allowing higher clock speeds to be achieved. CISC cores tend to be more complex but usually have better code density.

In practice, modern ISAs are a hybrid between the two approaches, with both simple and complex instructions.