RISC vs CISC

Contemporary usage of the terms RISC and CISC is muddy, but originally referred to the amount of operations a single instruction could (or should) do.

For example, swapping values between a register and a memory location on a RISC machine may be done as:

ld.w  x3,[x2]    ; 1 cycle
st.w  [x2],x1    ; 1 cycle
mv    x1,x3      ; 1 cycle

Whereas on a CISC machine it might be done as:

xchg  x1,[x2]    ; 3 cycles

RISC cores tend to be smaller and simpler, allowing higher clock speeds to be achieved. CISC cores tend to be more complex but usually have better code density.

CISC processors were often characterized by their extensive, microcode-based control units to coordinate the different steps that needed to be performed during an instruction, while RISC processors could get by with much simpler control units using only random logic. The space saved by the simpler control unit could be used to expand the register file, as in the ARM1.

A well-designed CISC instruction set encodes instructions compactly, using less memory. RISC architectures typically use the same size for each instruction, while CISC architectures typically vary the instruction length as needed, as well as performing several steps in a single instruction — both of which can be viewed as forms of compression. On the other hand, the "wasted" bits that are not necessary for a particular RISC instruction can be put to novel uses, such as the condition codes and integrated shifting in ARM.

In practice, modern ISAs are a hybrid between the two approaches, with both simple and complex instructions.