Instruction encoding

There are many different ways to encode instructions, all with their own tradeoffs.

Considerations

Fixed-width or variable-length

Even among variable-length ISAs there is a broad spectrum in complexity. For example, x86 is notorious for being difficult to decode. In contrast, RISC-V is also variable-length but trivial to decode.

Instruction density

Large instructions can encode many things but have poor density, while smaller instructions have good density but may not be able to encode many things.

Of particular note is the amount of directly addressable registers: a larger amount of registers requires more bits to encode, leaving less to encode other things.

Instruction formats

To reduce decoding complexity it is wise to define a few fixed formats, which all instructions should be defined in terms of.

Techniques

Variable-length encoding

To keep decoding variable-length instructions simple one can use a fixed prefix of a few bits.

For example, an ISA with 8, 16 and 24-bit instructions could be encoded as:

        23    16  15     8  7      0
 8-bit                      xxxxxxx0
16-bit            xxxxxxxx  xxxxxx01
24-bit  xxxxxxxx  xxxxxxxx  xxxxx011

Hardwired zero register

A substantial amount of instructions can be omitted by having a register which always reads 0.

Implicit destination registers

Instead of having explicitly named registers, one can instead have a queue of registers and address source registers relative to the "instruction distance".

Aside from being useful for out-of-order processors, this also avoids the need to encode a destination, freeing bits for other purposes.